Improved Test Pattern Generation for Sequential Circuits Using Implicit Enumeration
نویسندگان
چکیده
This paper describes ESSENTIAL, an efficient deterministic test pattern generation algorit.lim for synchronous sequential circuits. Its concept.ual strat,egy is based upon the combination of reverse time processing over time frames and forward processing wit,hin time frames. In addition to fully exploiting the beneficial methods that have successfully been used for combinational circuits by the ATG system SOCRATES, the proposed test generation approach comprises a new circuit model and several new techniques leading t.o a significant. improvement and acceleration of the determinist,ic t.est pa.t tern generation process.
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